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 EMIF06-1502M12
IPADTM 6 line low capacitance EMI filter and ESD protection in Micro QFN package
Main product characteristics
Where EMI filtering in ESD sensitive equipment is required:

12 11 10 9 8 7 GND
GND
1 2 3 4 5 6
LCD & CAMERA for Mobile phones Computers and printers Communication systems MCU Boards
Micro QFN 2.5 mm x 1.5 mm (bottom view)
Description
The EMIF06-1502M12 is a 6 line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins.
Pin configuration (top view)
1 Input 2 Input 3 Input 4 Input Output 12 Output 11 Output 10 Output 9 Output 8 Output 7
Benefits

5 Input 6 Input
EMI asymmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming: 2.5 mm x 1.5 mm Very thin package: 0.6 mm max High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4). High reliability offered by monolithic integration High reducing of parasitic elements through integration and wafer level packaging. Lead free package
Basic cell configuration
Input 170 Output
Typical line capacitance = 14 pF @ 2.5 V
Complies with following standards:
IEC 61000-4-2 level 4 input pins 15kV (air discharge) 8kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3 (all pins)
Order code
Part number EMIF06-1502M12 Marking E
TM: IPAD is a trademark of STMicroelectronics
July 2006
Rev 2
www.st.com
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Characteristics
EMIF06-1502M12
1
Table 1.
Symbol VPP Tj Top Tstg
Characteristics
Absolute ratings (limiting values at Tamb = 25 C unless otherwise specified)
Parameter ESD discharge IEC 61000-4-2 air discharge on input pins ESD discharge IEC 61000-4-2 contact discharge on input pins Junction temperature Operating temperature range Storage temperature range Value 15 8 125 -40 to + 85 -55 to +150 Unit kV C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic resistance Peak pulse current Series resistance between Input & Output Input capacitance per line
IPP VBR VCL VRM IRM IR VF V I IF
Symbol VBR IRM RI/O Cline IR = 1 mA VRM = 3 V per line Tolerance 10%
Test conditions
Min. 6
Typ. 8
Max. 10 100
Unit V nA pF
153
170 14
187
VR= 2.5 V DC, VOSC = 30 mV, F = 1 MHz
Figure 1.
0.00
S21(dB) attenuation measurement
dB
Figure 2.
dB
0.00 -10.00 -20.00
Analog cross talk measurements
-15.00
-30.00 -40.00 -50.00 -60.00
-30.00
-70.00 -80.00
F (Hz)
-45.00 100.0k 1.0M 10.0M 100.0M 1.0G
-90.00 -100.00 100.0k
F (Hz)
1.0M 10.0M 100.0M 1.0G
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EMIF06-1502M12
Ordering information scheme
Figure 3.
ESD response to IEC 61000-4-2 Figure 4. (+15 kV air discharge) on one input (Vin) and on one output (Vout)
Vin
ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input (Vin) and on one output (Vout)
C1 = 10 V/d
C1 = 10 V/d Vin Vout
C2 = 5 V/d
C2 = 5 V/d Vout 100 ns/d
100 ns/d
Figure 5.
Line capacitance versus reverse voltage applied (typical value)
CLINE(pF)
24 22 20 18 16 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0
VLINE(V) 2.5 3.0 3.5 4.0 4.5 5.0
2
Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Mx = Micro QFN x leads
yy
-
xxx z
Mx
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Package information
EMIF06-1502M12
3
Package information
Table 3. QFN 2.5 x 1.5 package dimensions
Dimensions Ref Millimeters MIN A A1 b D D2 E E2 e k L 0.20 0.25 0.30 0.35 0.30 1.70 0.50 0.00 0.15 TYP 0.55 0.02 0.18 2.50 1.80 1.50 0.40 0.40 0.08 0.10 0.12 0.14 0.50 0.12 1.90 0.67 MAX 0.60 0.05 0.25 MIN 0.20 0.00 0.06 inches TYP 0.22 0.01 0.07 0.98 0.71 0.59 0.16 0.16 0.24 0.75 MAX 0.24 0.02 0.10
Figure 6.
Footprint
Figure 7.
Marking
Dot: Pin 1 Identification X = Marking YWW= Data code (Y=year WW= week
XY ww
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EMIF06-1502M12 Figure 8. Tape and reel specification
2.0+/-0.05 4.00+/-0.1 f 1.5 +/- 0.1
Package information
1.75 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.05 3.5 +/- 0.05
0.75
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
8.1 +/- 0.1 8.1 +/- 0.1
XY ww
XY ww
XY ww
2.70 2.70
1.70 User direction of unreeling
4.00
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Recommendation on PCB assembly
EMIF06-1502M12
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil Opening Dimensions: L (Length), W (Width), T (Thickness).
L
T
W
b)
General Design Rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T Lx W Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for central exposed pad: Opening to footprint ratio is 50%. Example: Stencil opening L = 1224 m, W = 300 m, Footprint (see Figure 6.) L = 1800 m, W = 400 m. c) Stencil opening for leads: Opening to footprint ratio is 90%. Example: Stencil opening L = 570 m, W = 190 m, Footprint (see Figure 6.) L = 600 m, W = 200 m.
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended.
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EMIF06-1502M12 4.
Recommendation on PCB assembly
3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
4.5
Reflow profile
Temp.
Peak Temp. Liquidus Temp.
time
Pre-heating zone Soaking zone Reflow Cool Down zone zone
Tin-lead Alloy Parameters [SnPb - SnPbAg] Pre-heating rate Soaking temp. Soaking time Peak temperature Reflow time above liquidus Cool down rate 2.5 C/s 120-180 C 80-120 s 210-240 C 40-80 s < 6 C/s
Lead-Free Alloy [SnAgCu] 2.5 C/s 140-180 C 80-180 s 245-260 C 40-140 s < 6 C/s
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
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Ordering information
EMIF06-1502M12
5
Ordering information
Part number EMIF06-1502M12 Marking E Package Micro QFN Weight 6 mg Base qty 3000 Delivery mode Tape and reel (7")
6
Revision history
Date 12-Dec-2005 3-Jul-2006 Revision 1 2 Initial release. Reformatted to current standard. Changed Figure 1 to show improved results. Changes
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EMIF06-1502M12
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